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    DAC
    1993
    ACM
    96views Computer Architecture» more  DAC 1993»
    Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits
    13 years 9 months ago
    Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits
    Download  www.eecs.berkeley.edu
    Abhijit Dharchoudhury, Sung-Mo Kang
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    VLSID
    2003
    IEEE
    126views VLSI» more  VLSID 2003»
    Comparison of Heuristic Algorithms for Variable Partitioning in Circuit Implementation
    14 years 5 months ago
    Comparison of Heuristic Algorithms for Variable Partitioning in Circuit Implementation
    Download  www.ee.unlv.edu
    Functional decomposition is a process of splitting a complex circuit into smaller sub-circuits. This paper deals with the problem of determining the set of best free and bound var...
    Muthukumar Venkatesan, Henry Selvaraj
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    GLVLSI
    2005
    IEEE
    199views VLSI» more  GLVLSI 2005»
    Interconnect delay minimization through interlayer via placement in 3-D ICs
    13 years 11 months ago
    Interconnect delay minimization through interlayer via placement in 3-D ICs
    Download  www.ece.rochester.edu
    The dependence of the propagation delay of the interlayer 3-D interconnects on the vertical through via location and length is investigated. For a variable vertical through via lo...
    Vasilis F. Pavlidis, Eby G. Friedman
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    GLVLSI
    2009
    IEEE
    143views VLSI» more  GLVLSI 2009»
    Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
    13 years 9 months ago
    Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
    Download  www.cse.unt.edu
    In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
    Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
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    DAC
    2004
    ACM
    130views Computer Architecture» more  DAC 2004»
    A methodology to improve timing yield in the presence of process variations
    13 years 9 months ago
    A methodology to improve timing yield in the presence of process variations
    Download  www.cs.york.ac.uk
    The ability to control the variations in IC fabrication process is rapidly diminishing as feature sizes continue towards the sub-100 nm regime. As a result, there is an increasing...
    Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wa...
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