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    » Pessimism reduction in coupling-aware static timing analysis...
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    ASPDAC
    2008
    ACM
    104views Hardware» more  ASPDAC 2008»
    Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
    13 years 6 months ago
    Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
    Download  users.eecs.northwestern.edu
    With continued scaling of technology into nanometer regimes, the impact of coupling induced delay variations is significant. While several coupling-aware static timers have been pr...
    Debasish Das, Kip Killpack, Chandramouli V. Kashya...
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    ISQED
    2006
    IEEE
    85views Hardware» more  ISQED 2006»
    Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times
    13 years 11 months ago
    Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times
    Download  www.ece.rochester.edu
    — A methodology is proposed for interdependent setup time and hold time characterization of sequential circuits. Integrating the methodology into an industrial sign-off static ti...
    Emre Salman, Eby G. Friedman, Ali Dasdan, Feroze T...
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    VLSID
    2004
    IEEE
    111views VLSI» more  VLSID 2004»
    Improved Approach for Noise Propagation to Identify Functional Noise Violations
    14 years 5 months ago
    Improved Approach for Noise Propagation to Identify Functional Noise Violations
    Download  web.ics.purdue.edu
    This paper targets at reducing the crosstalk noise closure time by filtering the set of false violations. We propose two approaches to reduce the pessimism in the crosstalk noise ...
    Sachin Shrivastava, Dhanoop Varghese, Vikas Narang...
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    ASPDAC
    2006
    ACM
    157views Hardware» more  ASPDAC 2006»
    Delay modeling and static timing analysis for MTCMOS circuits
    13 years 11 months ago
    Delay modeling and static timing analysis for MTCMOS circuits
    Download  www.cecs.uci.edu
    - One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
    Naoaki Ohkubo, Kimiyoshi Usami
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    DAC
    2008
    ACM
    142views Computer Architecture» more  DAC 2008»
    On the role of timing masking in reliable logic circuit design
    14 years 5 months ago
    On the role of timing masking in reliable logic circuit design
    Download  www.eecs.umich.edu
    Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
    Smita Krishnaswamy, Igor L. Markov, John P. Hayes
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