4 search results - page 1 / 1 » Petri net modeling of gate and interconnect delays for power... |
DAC
2002
ACM
14 years 5 months ago
2002
ACM
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
WSC
2004
13 years 6 months ago
2004
Stochastic Petri nets (SPNs) have proven to be a powerful and enduring graphically-oriented framework for modelling and performance analysis of complex systems. This tutorial focu...
SLIP
2009
ACM
13 years 11 months ago
2009
ACM
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
ISQED
2003
IEEE
13 years 10 months ago
2003
IEEE
The importance of an interconnect pattern density model in ASIC design flow for a 90nm technology is presented. It is shown that performing the timing analysis at the worst-case c...