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ISCA
2003
IEEE
157views Hardware» more  ISCA 2003»
13 years 10 months ago
Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage
Scaling of CMOS technology causes the power supply voltages to fall and supply currents to rise at the same time as operating speeds are increasing. Falling supply voltages cause ...
Michael D. Powell, T. N. Vijaykumar
DATE
2009
IEEE
131views Hardware» more  DATE 2009»
13 years 11 months ago
An event-guided approach to reducing voltage noise in processors
Abstract—Supply voltage fluctuations that result from inductive noise are increasingly troublesome in modern microprocessors. A voltage “emergency”, i.e., a swing beyond tol...
Meeta Sharma Gupta, Vijay Janapa Reddi, Glenn H. H...
ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling
This paper proposes Noise-Direct, a design methodology for power integrity aware floorplanning, using microarchitectural feedback to guide module placement. Stringent power constr...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
13 years 11 months ago
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
HPCA
2009
IEEE
14 years 5 months ago
Voltage emergency prediction: Using signatures to reduce operating margins
Inductive noise forces microprocessor designers to sacrifice performance in order to ensure correct and reliable operation of their designs. The possibility of wide fluctuations i...
Vijay Janapa Reddi, Meeta Sharma Gupta, Glenn H. H...