23 search results - page 4 / 5 » Pipeline Gating: Speculation Control for Energy Reduction |
FPL
1995
Springer
13 years 8 months ago
1995
Springer
Although the energy required to perform a logic operation has continuously dropped at least by ten orders of magnitude since early vacuumtube electronics [1], the increasing clock ...
ISLPED
2009
ACM
13 years 11 months ago
2009
ACM
An energy efficient object recognition processor is proposed for real-time visual applications. Its energy efficiency is improved by lowering average power consumption while susta...
ASYNC
2004
IEEE
13 years 8 months ago
2004
IEEE
Register files of microprocessors have often been cited as performance bottlenecks and significant consumers of energy. The robust and modular nature of quasi-delay insensitive (Q...
ASPDAC
2009
ACM
13 years 8 months ago
2009
ACM
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...
ISCA
2008
IEEE
13 years 4 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...