85 search results - page 4 / 17 » Pipeline Iteration |
FCCM
2008
IEEE
14 years 16 days ago
2008
IEEE
Although pipelining or C-slowing an FPGA-based application can potentially dramatically improve the performance, this poses a question for conventional reconfigurable architecture...
ARITH
2005
IEEE
13 years 11 months ago
2005
IEEE
The pipelined CORDIC with linear approximation to rotation has been proposed to achieve reductions in delay, power and area; however, the schemes for rotation (multiplication) and...
IPPS
1998
IEEE
13 years 10 months ago
1998
IEEE
An effort to formalize the process of software pipelining loops with conditions is presented in this paper. A formal framework for scheduling such loops, based on representing set...
DAC
1993
ACM
13 years 10 months ago
1993
ACM
— We consider the resource-constrained scheduling of loops with interiteration dependencies. A loop is modeled as a data flow graph (DFG), where edges are labeled with the numbe...
CGO
2008
IEEE
14 years 16 days ago
2008
IEEE
In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and ne...