Tiling exploits temporal reuse carried by an outer loop of a loop nest to enhance cache locality. Loop skewing is typically required to make tiling legal. This restricts parallelis...
The possibility of pre-compensating images in a computer display according to the visual aberrations previously assessed in an optical system (e.g., the computer user’s eye) has...
Miguel Alonso Jr., Armando Barreto, Julie A. Jacko...
Since across-chip interconnect delays can exceed a clock cycle in nanometer technologies, it has become essential in high performance designs to add flip-flops on wires with multi...
Vidyasagar Nookala, Ying Chen, David J. Lilja, Sac...
Numerical non-robustness is a recurring phenomenon in scientific computing. It is primarily caused by numerical errors arising because of fixed-precision arithmetic in integer and...
This paper presents a fault tolerant design technique for the clockless wave pipeline. The specific architectural model investigated in this paper is the two-phase clockless asyn...
T. Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yon...