23 search results - page 2 / 5 » Platform-Based Testbench Generation |
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Transaction Level Modeling (TLM) is an emerging design practice for overcoming increasing design complexity. It aims at simplifying the design flow of embedded systems ning and v...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
This paper presents novel uses of functional interface specifications for verifying RTL designs. We demonstrate how a simulation environment, a correctness checker, and a function...
VLSI
2007
Springer
13 years 11 months ago
2007
Springer
— Software simulation remains the most used method for VHDL RTL functional verification. The functional verification process essentially consists of two parts. The first one is t...
FPL
2001
Springer
13 years 9 months ago
2001
Springer
Abstract. Visual data
ow environments are ideally suited for modeling digital signal processing (DSP) systems, as many DSP algorithms are most naturally speci ed by signal
ow gra...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
Functional verification of complex designs largely relies on the use of simulation in conjunction high-level verification languages (HVL) and test-bench automation (TBA) tools. In...