351 search results - page 5 / 71 » Plug-and-Play Architectural Design and Verification |
DAC
2005
ACM
14 years 6 months ago
2005
ACM
We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis. A practical bottleneck in the formal verification of hardware designs is the n...
FPGA
2005
ACM
13 years 11 months ago
2005
ACM
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
ISSTA
2006
ACM
13 years 11 months ago
2006
ACM
This paper addresses issues involved when an architect explore alternative designs including non-functional requirements; in our approach, non-functional requirements are expresse...
DAC
2007
ACM
14 years 6 months ago
2007
ACM
The trend to multi-core chip designs presents new challenges for design automation, while the increased reuse of components may offer solutions. This paper describes some of the k...