35 search results - page 1 / 7 » Power - Performance Optimization for Custom Digital Circuits |
IWSOC
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper explores the design and optimization of Quasi-Floating Gate MOS techniques to lowvoltage/low-power digital circuitry. The simulated power consumption of standard CMOS g...
CORR
2002
Springer
13 years 4 months ago
2002
Springer
-- This paper introduces a novel method for synthesizing digital circuits derived from Binary Decision Diagrams (BDDs) that can yield to reduction in power dissipation. The power r...
DATE
2009
IEEE
13 years 8 months ago
2009
IEEE
Traditional digital circuit synthesis flows start from an HDL behavioral definition and assume that circuit functions are almost completely defined, making don't-care conditio...
FPGA
2010
ACM
14 years 1 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
DAC
1998
ACM
13 years 9 months ago
1998
ACM
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...