37 search results - page 2 / 8 » Power Dissipation in Deep Submicron CMOS Digital Circuits |
ASPDAC
2010
ACM
13 years 2 months ago
2010
ACM
- Dynamic power consumption in CMOS circuits is usually estimated based on the number of signal transitions. However, when considering glitches, this is not accurate because narrow...
TVLSI
2002
13 years 4 months ago
2002
The estimation of average-power dissipation of a circuit through exhaustive simulation is impractical due to the large number of primary inputs and their combinations. In this brie...
ISLPED
1996
ACM
13 years 9 months ago
1996
ACM
In this paper, we present a new statistical technique for estimation of average power dissipation in digital circuits. Present statistical techniques estimate the average power ba...
TVLSI
2008
13 years 4 months ago
2008
-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
With scaling down to deep submicron and nanometer technologies, noise immunity is becoming a metric of the same importance as power, speed, and area. Smaller feature sizes, low vo...