166 search results - page 2 / 34 » Power Monitors: A Framework for System-Level Power Estimatio... |
ICCD
2006
IEEE
14 years 2 months ago
2006
IEEE
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chi...
CODES
2010
IEEE
13 years 2 months ago
2010
IEEE
This paper describes PowerBooter, an automated power model construction technique that uses built-in battery voltage sensors and knowledge of battery discharge behavior to monitor...
ICCAD
2008
IEEE
14 years 2 months ago
2008
IEEE
In this paper we propose an on-chip bus PMU which makes accurate estimates of system power consumption from a first-order linear power model by utilizing system-level activity in...
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
—Various instruction and transaction based power estimation techniques for processor and on-chip buses have been proposed in the past. In this paper, we propose a heterogeneous p...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Embedded DRAM (eDRAM) power-energy estimation is presented for system-on-a-chip (SOC) applications. The main feature is the signal swing based analytic (SSBA) model, which improve...