111 search results - page 1 / 23 » Power Optimization in Current Mode Circuits |
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
— This paper describes a new power minimizing method by optimizing supply voltage control and minimizing leakage in active and standby modes, respectively. In the active mode, th...
ISCAS
1999
IEEE
13 years 9 months ago
1999
IEEE
Current mode (ECL) logic has long been the option of choice in those applications requiring logic functions at multigigahertz rates. This trend continues despite the obvious very ...
JCSC
2002
13 years 4 months ago
2002
There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits re...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
— Power gating is widely accepted as an efficient way to suppress subthreshold leakage current. Yet, it suffers from gate leakage current, which grows very fast with scaling dow...