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VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
14 years 6 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
ISLPED
2006
ACM
83views Hardware» more  ISLPED 2006»
13 years 12 months ago
Considering process variations during system-level power analysis
Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various desig...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
ICCAD
1996
IEEE
151views Hardware» more  ICCAD 1996»
13 years 10 months ago
Expected current distributions for CMOS circuits
The analysis of CMOS VLSI circuit switching current has become an increasingly important and difficult task from both a VLSI design and simulation software perspective. This paper...
Dennis J. Ciplickas, Ronald A. Rohrer
ISPD
2005
ACM
130views Hardware» more  ISPD 2005»
13 years 11 months ago
Improved algorithms for link-based non-tree clock networks for skew variability reduction
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...
Anand Rajaram, David Z. Pan, Jiang Hu
DFT
2008
IEEE
117views VLSI» more  DFT 2008»
14 years 14 days ago
Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS
With each technology node shrink, a silicon chip becomes more susceptible to soft errors. The susceptibility further increases as the voltage is scaled down to save energy. Based ...
Vikas Chandra, Robert C. Aitken