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HPCA
2012
IEEE
12 years 13 days ago
Power balanced pipelines
Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been...
John Sartori, Ben Ahrens, Rakesh Kumar
MICRO
2000
IEEE
95views Hardware» more  MICRO 2000»
13 years 8 months ago
Very low power pipelines using significance compression
Data, addresses, and instructions are compressed by maintaining only significant bytes with two or three extension bits appended to indicate the significant byte positions. This s...
Ramon Canal, Antonio González, James E. Smi...
ISVLSI
2005
IEEE
113views VLSI» more  ISVLSI 2005»
13 years 10 months ago
Balancing System Level Pipelines with Stage Voltage Scaling
This paper presents an approach to dynamically balance the pipeline by scaling the stage supply voltages. Simulation results show that by such an approach about 50% improvement in...
Hui Guo, Sri Parameswaran
ASYNC
2005
IEEE
174views Hardware» more  ASYNC 2005»
13 years 10 months ago
Delay Insensitive Encoding and Power Analysis: A Balancing Act
Unprotected cryptographic hardware is vulnerable to a side-channel attack known as Differential Power Analysis (DPA). This attack exploits data-dependent power consumption of a co...
Konrad J. Kulikowski, Ming Su, Alexander B. Smirno...
CHES
2006
Springer
205views Cryptology» more  CHES 2006»
13 years 8 months ago
Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...
Konrad J. Kulikowski, Alexander B. Smirnov, Alexan...