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» Power distribution techniques for dual VDD circuits
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FPGA
2004
ACM
116views FPGA» more  FPGA 2004»
13 years 10 months ago
Low-power technology mapping for FPGA architectures with dual supply voltages
In this paper we study the technology mapping problem of FPGA architectures with dual supply voltages (Vdds) for power optimization. This is done with the guarantee that the mappi...
Deming Chen, Jason Cong, Fei Li, Lei He
ESSCIRC
2011
93views more  ESSCIRC 2011»
12 years 4 months ago
12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 volta
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...
Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomu...
ISLPED
2005
ACM
96views Hardware» more  ISLPED 2005»
13 years 10 months ago
Power-optimal repeater insertion considering Vdd and Vth as design freedoms
This work first presents an analytical repeater insertion method which optimizes power under delay constraint for a single net. This method finds the optimal repeater insertion ...
Yu Ching Chang, King Ho Tam, Lei He
FPGA
2005
ACM
122views FPGA» more  FPGA 2005»
13 years 10 months ago
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
Yan Lin, Fei Li, Lei He
TCAD
2010
97views more  TCAD 2010»
12 years 11 months ago
Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages
Abstract--This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done w...
Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li...