Sciweavers

5 search results - page 1 / 1
» Power estimation for architectural exploration of HW SW comm...
Sort
View
CODES
1999
IEEE
13 years 9 months ago
Power estimation for architectural exploration of HW/SW communication on system-level buses
The power consumption due to the HW/SW communication on system-level buses represents one of the major contributions to the overall power budget. A model to estimate the switching...
William Fornaciari, Donatella Sciuto, Cristina Sil...
ICMCS
2008
IEEE
168views Multimedia» more  ICMCS 2008»
13 years 12 months ago
A co-design platform for algorithm/architecture design exploration
The efficient implementation of multimedia algorithms, for the ever increasing complexity of the specifications and the emergence of the new generation of processing platforms c...
Christophe Lucarz, Marco Mattavelli, Julien Dubois
VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
13 years 11 months ago
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
TVLSI
1998
109views more  TVLSI 1998»
13 years 5 months ago
Power estimation of embedded systems: a hardware/software codesign approach
— The need for low-power embedded systems has become very significant within the microelectronics scenario in the most recent years. A power-driven methodology is mandatory duri...
William Fornaciari, Paolo Gubian, Donatella Sciuto...
CODES
2004
IEEE
13 years 9 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan