32 search results - page 3 / 7 » Power optimization of core-based systems by address bus enco... |
DATE
1999
IEEE
13 years 10 months ago
1999
IEEE
This paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed m...
CODES
2004
IEEE
13 years 9 months ago
2004
IEEE
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
GLVLSI
2003
IEEE
13 years 11 months ago
2003
IEEE
We propose an approach for reducing the energy consumption of address buses that targets both the switching and the crosstalk components of power dissipation. The method is based ...
CEC
2003
IEEE
13 years 11 months ago
2003
IEEE
In this paper we present two new approaches based on genetic algorithms (GA) to reduce power consumption by communication buses in an embedded system. The first approach makes it ...
ASPDAC
2001
ACM
13 years 9 months ago
2001
ACM
Power-efficient design requires reducing power dissipation in all parts of the design and during all stages of the design process subject to constraints on the system performance ...