9 search results - page 2 / 2 » Power reduction through iterative gate sizing and voltage sc... |
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
— Power gating is widely accepted as an efficient way to suppress subthreshold leakage current. Yet, it suffers from gate leakage current, which grows very fast with scaling dow...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract—On-chip power density and temperature are rising exponentially with decreasing feature sizes. This alarming trend calls for temperature management at every level of syst...
DAC
2009
ACM
14 years 5 months ago
2009
ACM
Exponentially rising cooling/packaging costs due to high power density call for architectural and software-level thermal management. Dynamic thermal management (DTM) techniques co...
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
We present a novel technique to exploit the power-performance tradeoff. The technique can be used stand-alone or in conjunction with dynamic voltage scaling, the mainstream techn...