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» Power-aware slack distribution for hierarchical VLSI design
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IPPS
2002
IEEE
13 years 10 months ago
Fast Inductance Extraction of Large VLSI Circuits
Accurate estimation of signal delay is critical to the design and verification of VLSI circuits. At very high frequencies, signal delay in circuits with small feature sizes is do...
Hemant Mahawar, Vivek Sarin, Weiping Shi
TCAD
2002
73views more  TCAD 2002»
13 years 5 months ago
A timing-constrained simultaneous global routing algorithm
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
Jiang Hu, Sachin S. Sapatnekar
DAC
2006
ACM
13 years 11 months ago
Hierarchical power distribution and power management scheme for a single chip mobile processor
A hierarchical power distribution methodology that enables more than dozen power domains in a chip and a power management scheme using 20 power domains are described. This method ...
Toshihiro Hattori, Takahiro Irita, Masayuki Ito, E...
IPPS
2006
IEEE
13 years 11 months ago
Node-disjoint paths in hierarchical hypercube networks
The hierarchical hypercube network is suitable for massively parallel systems. An appealing property of this network is the low number of connections per processor, which can faci...
Ruei-Yu Wu, J. G. Chang, Gen-Huey Chen
PC
2007
112views Management» more  PC 2007»
13 years 4 months ago
Service address routing: a network-embedded resource management layer for cluster computing
Service address routing is introduced as a novel and powerful paradigm for the integration of resource management functions into the interconnection fabric of cluster computers. S...
Isaac D. Scherson, Daniel S. Valencia, Enrique Cau...