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» Power-optimal pipelining in deep submicron technology
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ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
14 years 1 months ago
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
Nam Sung Kim, David Blaauw, Trevor N. Mudge
ISLPED
2004
ACM
78views Hardware» more  ISLPED 2004»
13 years 10 months ago
Power-optimal pipelining in deep submicron technology
Seongmoo Heo, Krste Asanovic
MICRO
1999
IEEE
105views Hardware» more  MICRO 1999»
13 years 9 months ago
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
Todd M. Austin
ICCAD
2002
IEEE
113views Hardware» more  ICCAD 2002»
14 years 1 months ago
Interconnect-aware high-level synthesis for low power
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
Lin Zhong, Niraj K. Jha
DAC
2003
ACM
14 years 5 months ago
Multilevel global placement with retiming
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous designs, this requires retiming and pipel...
Jason Cong, Xin Yuan