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DAC
2005
ACM
14 years 6 months ago
Architecture-adaptive range limit windowing for simulated annealing FPGA placement
Previous research has shown both theoretically and practically that simulated annealing can greatly benefit from the incorporation of an adaptive range limiting window to control ...
Kenneth Eguro, Scott Hauck, Akshay Sharma
ASPDAC
2005
ACM
90views Hardware» more  ASPDAC 2005»
13 years 7 months ago
Register placement for low power clock network
In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated...
Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qian...
ICCAD
2001
IEEE
103views Hardware» more  ICCAD 2001»
14 years 2 months ago
Interconnect Resource-Aware Placement for Hierarchical FPGAs
In this paper, we utilize Rent’s rule as an empirical measure for efficient clustering and placement of circuits on hierarchical FPGAs. We show that careful matching of design c...
Amit Singh, Ganapathy Parthasarathy, Malgorzata Ma...
ISPD
2005
ACM
145views Hardware» more  ISPD 2005»
13 years 11 months ago
NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs
In this paper, we present a hierarchical ratio partitioning based placement algorithm for large-scale mixed-size designs. The placement algorithm consists of three steps: global p...
Tung-Chieh Chen, Tien-Chang Hsu, Zhe-Wei Jiang, Ya...
CODES
2007
IEEE
14 years 5 days ago
Secure FPGA circuits using controlled placement and routing
In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an ex...
Pengyuan Yu, Patrick Schaumont