38 search results - page 1 / 8 » Precise RSSI with High Process Variation Tolerance |
ISCAS
2007
IEEE
13 years 10 months ago
2007
IEEE
— A receiving signal strength indicator (RSSI) built with transconductance amplifiers is presented. The RSSI achieves high tolerance to process variations by utilizing the unique...
GLVLSI
2008
IEEE
13 years 5 months ago
2008
IEEE
This paper presents a process variation tolerant, SoC ready, 1GS/s, 6 bit flash analog-to-digital converter (ADC) suitable for integration into nanoscale digital CMOS technologie...
ISCAS
2008
IEEE
13 years 10 months ago
2008
IEEE
— In a nanoscale technology, memory bits are highly susceptible to process variation induced read/write failures. To address the above problem, in this paper a new memory cell is...
TVLSI
2010
12 years 11 months ago
2010
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise mar...
DAC
1996
ACM
13 years 8 months ago
1996
ACM
1- A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This met...