Sciweavers

13 search results - page 1 / 3
» Predicting performance potential of modern DSPs
Sort
View
DAC
2000
ACM
14 years 5 months ago
Predicting performance potential of modern DSPs
Naji Ghazal, A. Richard Newton, Jan M. Rabaey
APCSAC
2006
IEEE
13 years 11 months ago
A Study of the Performance Potential for Dynamic Instruction Hints Selection
Abstract. Instruction hints have become an important way to communicate compile-time information to the hardware. They can be generated by the compiler and the post-link optimizer ...
Rao Fu, Jiwei Lu, Antonia Zhai, Wei-Chung Hsu
CODES
2006
IEEE
13 years 11 months ago
Challenges in exploitation of loop parallelism in embedded applications
Embedded processors have been increasingly exploiting hardware parallelism. Vector units, multiple processors or cores, hyper-threading, special-purpose accelerators such as DSPs ...
Arun Kejariwal, Alexander V. Veidenbaum, Alexandru...
IEEEPACT
2002
IEEE
13 years 10 months ago
A Framework for Parallelizing Load/Stores on Embedded Processors
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
Xiaotong Zhuang, Santosh Pande, John S. Greenland ...
ANCS
2005
ACM
13 years 10 months ago
Segmented hash: an efficient hash table implementation for high performance networking subsystems
Hash tables provide efficient table implementations, achieving O(1), query, insert and delete operations at low loads. However, at moderate or high loads collisions are quite freq...
Sailesh Kumar, Patrick Crowley