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ASPDAC
2006
ACM
103views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Prefetching-aware cache line turnoff for saving leakage energy
Abstract— While numerous prior studies focused on performance and energy optimizations for caches, their interactions have received much less attention. This paper studies this i...
Ismail Kadayif, Mahmut T. Kandemir, Feihui Li
ICPP
2009
IEEE
13 years 2 months ago
Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this c...
Matteo Monchiero, Ramon Canal, Antonio Gonzá...
TC
2008
13 years 4 months ago
On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance
This paper describes a new on-demand wake-up prediction policy for reducing leakage power. The key insight is that branch prediction can be used to selectively wake up only the nee...
Sung Woo Chung, Kevin Skadron
APCSAC
2006
IEEE
13 years 11 months ago
Using Branch Prediction Information for Near-Optimal I-Cache Leakage
This paper describes a new on-demand wakeup prediction policy for instruction cache leakage control that achieves better leakage savings than prior policies, and avoids the perform...
Sung Woo Chung, Kevin Skadron
ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
13 years 6 months ago
A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation
- Exceptionally leaky transistors are increasingly more frequent in nano-scale technologies due to lower threshold voltage and its increased variation. Such leaky transistors may e...
Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura