500 search results - page 100 / 100 » Process Scheduling for the Parallel Desktop |
MICRO
2010
IEEE
13 years 4 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
JPDC
2006
13 years 5 months ago
2006
Minimization of the execution time of an iterative application in a heterogeneous parallel computing environment requires an appropriate mapping scheme for matching and scheduling...
ESCIENCE
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper we present an initial analysis of job failures in a large-scale data-intensive Grid. Based on three representative periods in production, we characterize the interar...
HICSS
2003
IEEE
13 years 11 months ago
2003
IEEE
The underlying structure of why and how consumers value reliability of electric service is explored, together with the technological options and cost characteristics for the provi...