51 search results - page 10 / 11 » Process Variation Tolerant 3T1D-Based Cache Architectures |
DAC
2009
ACM
13 years 10 months ago
2009
ACM
Process scaling has given designers billions of transistors to work with. As feature sizes near the atomic scale, extensive variation and wearout inevitably make margining unecono...
INFOCOM
2002
IEEE
13 years 10 months ago
2002
IEEE
— We consider the problem of distributing high-quality video signals over IP multicast in large Local Area Networks (LANs), under realtime delay constraints, and with software-on...
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
DSN
2007
IEEE
13 years 11 months ago
2007
IEEE
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...