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» Process variation aware cache leakage management
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ISLPED
2006
ACM
119views Hardware» more  ISLPED 2006»
13 years 11 months ago
Process variation aware cache leakage management
In a few technology generations, limitations of fabrication processes will make accurate design time power estimates a daunting challenge. Static leakage current which comprises a...
Ke Meng, Russ Joseph
ICCD
2007
IEEE
180views Hardware» more  ICCD 2007»
14 years 1 months ago
Improving the reliability of on-chip data caches under process variations
On-chip caches take a large portion of the chip area. They are much more vulnerable to parameter variation than smaller units. As leakage current becomes a significant component ...
Wei Wu, Sheldon X.-D. Tan, Jun Yang 0002, Shih-Lie...
ISVLSI
2008
IEEE
156views VLSI» more  ISVLSI 2008»
13 years 11 months ago
Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways
The share of leakage in cache power consumption increases with technology scaling. Choosing a higher threshold voltage (Vth) and/or gate-oxide thickness (Tox) for cache transistor...
Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihar...
DAC
2009
ACM
14 years 5 months ago
Process variation characterization of chip-level multiprocessors
Within-die variation in leakage power consumption is substantial and increasing for chip-level multiprocessors (CMPs) and multiprocessor systems-on-chip. Dealing with this problem...
Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, ...
VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
14 years 5 months ago
Temperature and Process Variations Aware Power Gating of Functional Units
Technology scaling has resulted in an exponential increase in the leakage power as well as the variations in leakage power of fabricated chips. Functional units (FUs), like Intege...
Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sar...