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DFT
2009
IEEE
178views VLSI» more  DFT 2009»
14 years 2 days ago
Soft Core Embedded Processor Based Built-In Self-Test of FPGAs
This paper presents the first implementation of Built-In Self-Test (BIST) of Field Programmable Gate Arrays (FPGAs) using a soft core embedded processor for reconfiguration of the...
Bradley F. Dutton, Charles E. Stroud
ITC
2003
IEEE
123views Hardware» more  ITC 2003»
13 years 10 months ago
Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores
1 This paper addresses the issue of testing and diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper that follows a progr...
Davide Appello, Paolo Bernardi, Alessandra Fudoli,...
DATE
2003
IEEE
104views Hardware» more  DATE 2003»
13 years 10 months ago
A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories
In this paper we present a microprocessor-based approach suitable for embedded flash memory testing in a System-on-achip (SOC) environment. The main novelty of the approach is the...
Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza ...
CSREAESA
2009
13 years 6 months ago
Built-In Self-Test of Embedded SEU Detection Cores in Virtex-4 and Virtex-5 FPGAs
A Built-In Self-Test (BIST) approach is presented for the Internal Configuration Access Port (ICAP) and Frame Error Correcting Code (ECC) logic cores embedded in Xilinx Virtex-4 an...
Bradley F. Dutton, Charles E. Stroud
MTDT
2002
IEEE
108views Hardware» more  MTDT 2002»
13 years 10 months ago
A Fault Modeling Technique to Test Memory BIST Algorithms
The amount of memory being embedded on chip is growing rapidly. This strongly implies that memory Built-in-self-test (BIST) logic assumes utmost importance amongst all on chip sel...
Raja Venkatesh, Sailesh Kumar, Joji Philip, Sunil ...