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DATE
2008
IEEE
223views Hardware» more  DATE 2008»
13 years 11 months ago
Cooperative Safety: a Combination of Multiple Technologies
—Governmental Transportation Authorities' interest in Car to Car and Car to Infrastructure has grown dramatically over the last few years in order to increase the road safet...
Raffaele Penazzi, Piergiorgio Capozio, Martin Dunc...
DDECS
2007
IEEE
201views Hardware» more  DDECS 2007»
13 years 11 months ago
Built in Defect Prognosis for Embedded Memories
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskaran...
IESS
2007
Springer
120views Hardware» more  IESS 2007»
13 years 11 months ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...
VLSID
2006
IEEE
183views VLSI» more  VLSID 2006»
13 years 11 months ago
Design Challenges for High Performance Nano-Technology
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
Goutam Debnath, Paul J. Thadikaran
ISLPED
2004
ACM
139views Hardware» more  ISLPED 2004»
13 years 10 months ago
Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...
Kim M. Hazelwood, David Brooks