77 search results - page 2 / 16 » Promising Directions in Hardware Design Verification (invite... |
ISQED
2007
IEEE
14 years 1 days ago
2007
IEEE
Design verification has become a bottleneck of modern designs. Recently, simulation-based random verification has attracted a lot of interests due to its effectiveness in uncoveri...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
In the way they cope with variability, present-day methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important as...
DATE
2006
IEEE
13 years 12 months ago
2006
IEEE
Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden a...
DATE
2007
IEEE
14 years 3 days ago
2007
IEEE
: - The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to...
GLVLSI
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper describes a new design for a hardware accelerator to support grid-based Maze Routing. Based on the direct mapped approach of Breuer and Shamsa [3], this work refines th...