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GLVLSI
2002
IEEE

A new look at hardware maze routing

10 years 6 months ago
A new look at hardware maze routing
This paper describes a new design for a hardware accelerator to support grid-based Maze Routing. Based on the direct mapped approach of Breuer and Shamsa [3], this work refines their design to substantially reduce the hardware requirements of each processing eleemnt while at the same time adding support for mulitilayer routing and fast iterative routing. An initial implementation has been developed in VHDL, and initial results show promise for its implementation using an ASIC, custom chip, or FPGA.
John A. Nestor
Added 14 Jul 2010
Updated 14 Jul 2010
Type Conference
Year 2002
Where GLVLSI
Authors John A. Nestor
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