24 search results - page 2 / 5 » Pseudo-Random Pattern Generator Design for Column-Matching B... |
IOLTS
2000
IEEE
13 years 9 months ago
2000
IEEE
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
| This paper reports the design of a Test Pattern Generator (TPG) for VLSI circuits. The onchip TPG is so designed that it generates test patterns while avoiding generation of a gi...
ITC
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K t...
ATS
2000
IEEE
13 years 9 months ago
2000
IEEE
VLSID
2003
IEEE
14 years 5 months ago
2003
IEEE
This paper introduces a Built-In Self Test (BIST) structure referred to as Universal BIST (UBIST). The Test Pattern Generator (TPG) of the proposed UBIST is designed to generate an...