At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too hi...
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
The application of Dynamic Voltage Scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faul...
Noohul Basheer Zain Ali, Mark Zwolinski, Bashir M....
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...
Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vi...
A method of generating test pairs for the delay faults is presented in this paper. The modification of the MISR register gives the source of test pairs. The modification of this r...