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» Quality considerations in delay fault testing
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TCAD
2008
114views more  TCAD 2008»
13 years 4 months ago
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns
At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too hi...
Zhanglei Wang, Krishnendu Chakrabarty
VTS
1996
IEEE
112views Hardware» more  VTS 1996»
13 years 9 months ago
Optimal voltage testing for physically-based faults
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
Yuyun Liao, D. M. H. Walker
ETS
2006
IEEE
129views Hardware» more  ETS 2006»
13 years 11 months ago
Dynamic Voltage Scaling Aware Delay Fault Testing
The application of Dynamic Voltage Scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faul...
Noohul Basheer Zain Ali, Mark Zwolinski, Bashir M....
VLSID
1996
IEEE
110views VLSI» more  VLSID 1996»
13 years 9 months ago
On test coverage of path delay faults
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...
Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vi...
DDECS
2007
IEEE
90views Hardware» more  DDECS 2007»
13 years 8 months ago
Test Pattern Generator for Delay Faults
A method of generating test pairs for the delay faults is presented in this paper. The modification of the MISR register gives the source of test pairs. The modification of this r...
Tomasz Rudnicki, Andrzej Hlawiczka