41 search results - page 2 / 9 » Quantifying Error in Dynamic Power Estimation of CMOS Circui... |
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrou...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
DATE
1997
IEEE
13 years 9 months ago
1997
IEEE
: In this paper, we present a new dynamic power estimation method that produces accurate power measures at considerably faster run times. The approach uses an enhanced switch-level...
ISCAS
1995
IEEE
13 years 8 months ago
1995
IEEE
— This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits. The model is based on Berkeley S...
TCAD
1998
13 years 5 months ago
1998
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the noti...