—FPGAs are widely used for evaluating the error-floor performance of LDPC (low-density parity check) codes. We propose a scalable vector decoder for FPGA-based implementation of...
Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Ake...
— For decoding low-density parity-check (LDPC) codes on discrete memoryless channels, a method to quantize messages and to find message-passing decoding functions for the variab...
Brian M. Kurkoski, Kazuhiko Yamaguchi, Kingo Kobay...
A Split decoding algorithm is proposed which divides each row of the parity check matrix into two or multiple nearly-independent simplified partitions. The proposed method signific...
— We present a new multi-rate architecture for decoding irregular LDPC codes in IEEE 802.16e WiMax standard. The proposed architecture utilizes the value–reuse property of offs...
Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary, Moha...
— This paper proposes a new approach for decoding LDPC codes over MISO channels. Since in an nT × 1 MISO system with a modulation of alphabet size 2M, nT transmitted symbols are...
Amir H. Djahanshahi, Paul H. Siegel, Laurence B. M...