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    DAC
    2007
    ACM
    131views Computer Architecture» more  DAC 2007»
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    14 years 6 months ago
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    Download  cobweb.ecn.purdue.edu
    This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
    Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
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    CEC
    2008
    IEEE
    118views Artificial Intelligence» more  CEC 2008»
    Automatic model type selection with heterogeneous evolution: An application to RF circuit block modeling
    13 years 11 months ago
    Automatic model type selection with heterogeneous evolution: An application to RF circuit block modeling
    Download  www.sumo.intec.ugent.be
    — Many complex, real world phenomena are difficult to study directly using controlled experiments. Instead, the use of computer simulations has become commonplace as a cost effe...
    Dirk Gorissen, Luciano De Tommasi, Jeroen Croon, T...
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    CASES
    2006
    ACM
    173views System Software» more  CASES 2006»
    Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations
    13 years 11 months ago
    Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations
    Download  www.eecs.harvard.edu
    Rising interest in the applications of wireless sensor networks has spurred research in the development of computing systems for lowthroughput, energy-constrained applications. Un...
    Mark Hempstead, Gu-Yeon Wei, David Brooks
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    WSC
    2007
    166views Modeling And Simulation» more  WSC 2007»
    Optimizing time warp simulation with reinforcement learning techniques
    13 years 7 months ago
    Optimizing time warp simulation with reinforcement learning techniques
    Download  www.informs-sim.org
    Adaptive Time Warp protocols in the literature are usually based on a pre-defined analytic model of the system, expressed as a closed form function that maps system state to cont...
    Jun Wang, Carl Tropper
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    ICCAD
    2006
    IEEE
    127views Hardware» more  ICCAD 2006»
    Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
    14 years 2 months ago
    Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
    Download  www.cerc.utexas.edu
    Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
    Murari Mani, Ashish Kumar Singh, Michael Orshansky
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