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» RC Interconnect Optimization Under the Elmore Delay Model
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ISPD
1997
ACM
186views Hardware» more  ISPD 1997»
13 years 9 months ago
EWA: exact wiring-sizing algorithm
The wire sizing problem under inequality Elmore delay constraints is known to be posynomial, hence convex under an exponential variable-transformation. There are formal methods fo...
Rony Kay, Gennady Bucheuv, Lawrence T. Pileggi
ISCAS
2006
IEEE
82views Hardware» more  ISCAS 2006»
13 years 11 months ago
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing
– This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that crosscapacitances are ...
Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
ICCAD
2003
IEEE
113views Hardware» more  ICCAD 2003»
14 years 1 months ago
Retiming with Interconnect and Gate Delay
In this paper, we study the problem of retiming of sequential circuits with both interconnect and gate delay. Most retiming algorithms have assumed ideal conditions for the non-lo...
Chris C. N. Chu, Evangeline F. Y. Young, Dennis K....
DAC
1995
ACM
13 years 8 months ago
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...
Noel Menezes, Satyamurthy Pullela, Lawrence T. Pil...
DAC
1999
ACM
14 years 5 months ago
Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
Chung-Ping Chen, Noel Menezes