39 search results - page 2 / 8 » Re-mapping for low power under tight timing constraints |
DAC
1997
ACM
13 years 9 months ago
1997
ACM
We present a system-level approach for power optimization under a set of user specified costs and timing constraints of hard real-time designs. The approach optimizes all three d...
RTAS
2000
IEEE
13 years 9 months ago
2000
IEEE
—Many embedded systems operate under severe power and energy constraints. Voltage clock scaling is one mechanism by which energy consumption may be reduced: It is based on the fa...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
Power consumption has gained much saliency in circuit design recently. One design problem is modelled as ”Under a timing constraint, to minimize power as much as possible”. Pr...
ISLPED
2009
ACM
13 years 11 months ago
2009
ACM
Increasing power densities and the high cost of low thermal resistance packages and cooling solutions make it impractical to design processors for worst-case temperature scenarios...
CORR
2008
Springer
13 years 5 months ago
2008
Springer
We investigate the limits of communication over the discrete-time Additive White Gaussian Noise (AWGN) channel, when the channel output is quantized using a small number of bits. W...