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» ReCycle: : pipeline adaptation to tolerate process variation
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ISCA
2007
IEEE
117views Hardware» more  ISCA 2007»
13 years 11 months ago
ReCycle: : pipeline adaptation to tolerate process variation
Process variation affects processor pipelines by making some stages slower and others faster, therefore exacerbating pipeline unbalance. This reduces the frequency attainable by t...
Abhishek Tiwari, Smruti R. Sarangi, Josep Torrella...
ASPDAC
2006
ACM
104views Hardware» more  ASPDAC 2006»
13 years 9 months ago
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar proces
- Technology scaling and sub-wavelength optical lithography is associated with significant process variations. We propose a self-adaptive variable supply-voltage scaling (SAVS) tec...
Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh
ASPDAC
2010
ACM
143views Hardware» more  ASPDAC 2010»
13 years 3 months ago
A low latency wormhole router for asynchronous on-chip networks
Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous wormhole route...
Wei Song, Doug Edwards
BMCBI
2004
117views more  BMCBI 2004»
13 years 5 months ago
CisOrtho: A program pipeline for genome-wide identification of transcription factor target genes using phylogenetic footprinting
Background: All known genomes code for a large number of transcription factors. It is important to develop methods that will reveal how these transcription factors act on a genome...
Henry R. Bigelow, Adam S. Wenick, Allan Wong, Oliv...
DATE
2008
IEEE
82views Hardware» more  DATE 2008»
13 years 11 months ago
Variation tolerant NoC design by means of self-calibrating links
We present the implementation and analysis of a variation tolerant version of a switch-to-switch link in a NoC. The goal is to tolerate the effects of process variations on NoC ar...
Simone Medardoni, Marcello Lajolo, Davide Bertozzi