174 search results - page 2 / 35 » Reclocking for high-level synthesis |
VLSID
2003
IEEE
14 years 5 months ago
2003
IEEE
The design of modern complex embedded systems require a high level of abstraction of the design. The SimnML[1] is a specification language to model processors for such designs. Se...
ICCAD
2003
IEEE
14 years 2 months ago
2003
IEEE
This work is a contribution to high level synthesis for low power systems. While device feature size decreases, interconnect power becomes a dominating factor. Thus it is importan...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Loop unrolling is a well-known compiler optimization that can lead to significant performance improvements. When used in High Level Synthesis (HLS) unrolling can affect the contr...
DAC
2001
ACM
14 years 6 months ago
2001
ACM
The quality of synthesis results for most high level synthesis approaches is strongly a ected by the choice of control ow through conditions and loops in the input description. In...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
High level synthesis transformations play a major part in shaping the properties of the final circuit. However, most optimizations are performed without much knowledge of the fina...