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MJ
2006
145views more  MJ 2006»
13 years 5 months ago
A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems
In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity ...
Michalis D. Galanis, Athanasios Milidonis, Athanas...
FCCM
2009
IEEE
106views VLSI» more  FCCM 2009»
13 years 9 months ago
Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators
Modern use of FPGAs as hardware accelerators involves the partial reconfiguration of hardware resources as the application executes. In this paper, we present a polynomial time al...
Joon Edward Sim, Weng-Fai Wong, Jürgen Teich
ARC
2009
Springer
127views Hardware» more  ARC 2009»
13 years 9 months ago
Parametric Design for Reconfigurable Software-Defined Radio
Run-time reconfigurable FPGAs are powerful platforms for realising software-defined radio systems. This paper introduces a parametric approach to designing such systems based on ap...
Tobias Becker, Wayne Luk, Peter Y. K. Cheung
DATE
1999
IEEE
194views Hardware» more  DATE 1999»
13 years 9 months ago
CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems
Dynamically reconfigurable embedded systems offer potential for higher performance as well as adaptability to changing system requirements at low cost. Such systems employ run-tim...
Bharat P. Dav
IPPS
2006
IEEE
13 years 11 months ago
Communication concept for adaptive intelligent run-time systems supporting distributed reconfigurable embedded systems
Reconfigurable computing systems have already shown their abilities to accelerate embedded hardware/ software systems. Since standard processor-based embedded applications have co...
M. Ullmann, J. Becker