29 search results - page 2 / 6 » Reducing Register Pressure Through LAER Algorithm |
IEEEPACT
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper discusses a register bank assignment problem for a popular network processor--Intel's IXP. Due to limited data paths, the network processor has a restriction that ...
HPCA
1998
IEEE
13 years 9 months ago
1998
IEEE
A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late stage in the pi...
MICRO
1997
IEEE
13 years 9 months ago
1997
IEEE
The multicluster architecture that we introduce offers a decentralized, dynamically-scheduled architecture, in which the register files, dispatch queue, and functional units of t...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
- Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult pro...
GLVLSI
2007
IEEE
13 years 8 months ago
2007
IEEE
Application-specific instruction set processor (ASIP) has become an important design choice for embedded systems. It can achieve both high flexibility offered by the base processo...