39 search results - page 1 / 8 » Reducing bus delay in submicron technology using coding |
ASPDAC
2001
ACM
13 years 8 months ago
2001
ACM
ct,. In this paper we study the delay associated with transmission of data through busses. Previous work in this area has presented models for delay assuming a distributed wire mqd...
DAC
1999
ACM
13 years 9 months ago
1999
ACM
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...
CODES
2006
IEEE
13 years 11 months ago
2006
IEEE
In deep sub-micron technology, the crosstalk effect between adjacent wires has become an important issue, especially between long on-chip buses. This effect leads to the increas...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
In this paper, we propose an adaptive low-power bus encoding algorithm based on weighted code mapping (WCM) and the delayed bus technique. The WCM algorithm transforms an original...