4 search results - page 1 / 1 » Reducing clock skew variability via cross links |
DAC
2004
ACM
14 years 5 months ago
2004
ACM
Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Non-tree clock network has been recognized as a promising approac...
ISPD
2005
ACM
13 years 10 months ago
2005
ACM
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...
DAC
2009
ACM
13 years 11 months ago
2009
ACM
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
Most existing performance-driven and clock routing algorithms can not guarantee performance after all nets are routed. This paper proposes a new post routing approach which can re...