18 search results - page 4 / 4 » Reducing leakage power in peripheral circuits of L2 caches |
TVLSI
2008
13 years 4 months ago
2008
Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors...
TC
2008
13 years 4 months ago
2008
This paper describes a new on-demand wake-up prediction policy for reducing leakage power. The key insight is that branch prediction can be used to selectively wake up only the nee...
MICRO
2008
IEEE
13 years 11 months ago
2008
IEEE
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...