29 search results - page 1 / 6 » Reducing misspeculation overhead for module-level speculativ... |
CF
2005
ACM
13 years 6 months ago
2005
ACM
Thread-level speculative execution is a technique that makes it possible for a wider range of single-threaded applications to make use of the processing resources in a chip multip...
IPPS
2003
IEEE
13 years 10 months ago
2003
IEEE
Exploiting speculative thread-level parallelism across modules, e.g., methods, procedures, or functions, have shown promise. However, misspeculations and task creation overhead ar...
MICRO
2008
IEEE
13 years 11 months ago
2008
IEEE
The advent of multicores presents a promising opportunity for speeding up sequential programs via profile-based speculative parallelization of these programs. In this paper we pr...
ASPLOS
2004
ACM
13 years 10 months ago
2004
ACM
Pipeline flushes are becoming increasingly expensive in modern microprocessors with large instruction windows and deep pipelines. Selective re-execution is a technique that can r...
ISCAPDCS
2003
13 years 6 months ago
2003
This paper presents the Dynamic Simultaneous Multithreaded Architecture (DSMT). DSMT efficiently executes multiple threads from a single program on a SMT processor core. To accomp...