16 search results - page 2 / 4 » Reducing peak power with a table-driven adaptive processor c... |
CODES
2007
IEEE
13 years 11 months ago
2007
IEEE
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...
VEE
2006
ACM
13 years 11 months ago
2006
ACM
During recent years, microprocessor energy consumption has been surging and efforts to reduce power and energy have received a lot of attention. At the same time, virtual executio...
ISCA
2008
IEEE
13 years 11 months ago
2008
IEEE
Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introd...
IEEEPACT
2008
IEEE
13 years 11 months ago
2008
IEEE
The emergence of power as a first-class design constraint has fueled the proposal of a growing number of run-time power optimizations. Many of these optimizations trade-off power...
MICRO
2009
IEEE
13 years 12 months ago
2009
IEEE
As technology scaling drives the number of processor cores upward, current on-chip routers consume substantial portions of chip area and power budgets. Since existing research has...