26 search results - page 2 / 6 » Reducing the Scheduling Critical Cycle Using Wakeup Predicti... |
ISCA
2003
IEEE
13 years 10 months ago
2003
IEEE
Current-generation microprocessors are designed to process instructions with one and two source operands at equal cost. Handling two source operands requires multiple ports for ea...
MICRO
1997
IEEE
13 years 9 months ago
1997
IEEE
The multicluster architecture that we introduce offers a decentralized, dynamically-scheduled architecture, in which the register files, dispatch queue, and functional units of t...
ISCA
2007
IEEE
13 years 11 months ago
2007
IEEE
From multiprocessor scale-up to cache sizes to the number of reorder-buffer entries, microarchitects wish to reap the benefits of more computing resources while staying within po...
APCSAC
2005
IEEE
13 years 11 months ago
2005
IEEE
In order to enhance the performance of a computer, most modern processors use superscalar architecture and raise the clock frequency. Superscalar architecture can execute more than...
ISCA
2002
IEEE
13 years 10 months ago
2002
IEEE
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...