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» Redundancy in Instruction Sequences of Computer Programs
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DATE
2003
IEEE
97views Hardware» more  DATE 2003»
13 years 11 months ago
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
G. Surendra, Subhasis Banerjee, S. K. Nandy
IEEEPACT
2008
IEEE
14 years 14 days ago
Skewed redundancy
Technology scaling in integrated circuits has consistently provided dramatic performance improvements in modern microprocessors. However, increasing device counts and decreasing o...
Gordon B. Bell, Mikko H. Lipasti
SAMOS
2004
Springer
13 years 11 months ago
The Molen Programming Paradigm
— In this paper we present the Molen programming paradigm, which is a sequential consistency paradigm for programming Custom Computing Machines (CCM). The programming paradigm al...
Stamatis Vassiliadis, Georgi Gaydadjiev, Koen Bert...
ISCA
2002
IEEE
93views Hardware» more  ISCA 2002»
13 years 11 months ago
Transient-Fault Recovery Using Simultaneous Multithreading
We propose a scheme for transient-fault recovery called Simultaneously and Redundantly Threaded processors with Recovery (SRTR) that enhances a previously proposed scheme for tran...
T. N. Vijaykumar, Irith Pomeranz, Karl Cheng
IEEEPACT
2002
IEEE
13 years 11 months ago
Effective Compilation Support for Variable Instruction Set Architecture
Traditional compilers perform their code generation tasks based on a fixed, pre-determined instruction set. This paper describes the implementation of a compiler that determines ...
Jack Liu, Timothy Kong, Fred C. Chow